Method of forming an isolation layer and method of manufacturing a trench capacitor

ABSTRACT

A two-step etch process is used to form a vertical collar oxide within the upper portion of a trench capacitor. The first step uses CF 4 /SiF 4 /O 2  chemistry and ends when the bottom of the collar within the trench is opened although a thin oxide layer still remains on the surface of the PAD-nitride. The second etch step uses C 4 F 8  chemistry to completely remove the remaining silicon oxide layer. The process provides a good uniformity in thickness of the PAD-nitride layer and sufficient collar oxide thickness in the very top section of the collar oxide. The process is applicable for manufacturing deep trench capacitors for DRAM devices.

[0001] The invention refers to a method of forming an isolation layer onthe sidewalls of a trench whereby a semiconductior wafer that comprisesa substrate is provided, the substrate having a first isolation layerarranged on a main surface of the substrate and having a trench arrangedwithin the substrate. A second isolation layer is being deposited on thewafer, the horizontal portions of the second isolation layer are to beetched. The invention further refers to a method of manufacturing atrench capacitor that uses the above method of forming an isolationlayer on the sidewalls of the trench.

[0002] In the field ofmanufacturing dynamic random access memories(DRAMs) the storage capacitor is formed as a deep trench capacitorwithin the semiconductor substrate. The lower portion of the trenchcomprises the storage node having one plate of the capacitor within thesubstrate, having the dielectric layer arranged on the sidewalls of thelower portion of the trench and having the second electrode arrangedpreferably as a polysilicon filling material within the trench. Theupper portion of the trench is isolated from the substrate by aso-called collar isolation, preferably a thick silicon oxide collarlayer. In the sequence of precess steps for the manufacturing of thetrench capacitor, the semiconductor wafer is provided with the storagenode already completed. At this point, the lower portion of the trenchhas the dielectric layer arranged on its sidewalls and is filled withpolysilicon. On the surface of the wafer, a PAD-silicon nitride layer isalready deposited. The upper portion of the deep trench is still openand subject to further processing. Now, a conformal isolation layer,preferably a silicon oxide layer, is deposited on the wafer. As aresult, the conformal layer of silicon oxide is present on the sidewallsof the upper portion of the trench, on the bottom surface of said upperportion of the trench, and on the silicon nitride layer on the mainsurface of the semiconductor wafer. Within the upper portion of thetrench, the silicon oxide layer is directly deposited onto the upper endof the polysilicon filling material which is arranged in the lowerportion of the deep trench. At this stage, the process of manfacturingthe trench capacitor continues with the removal of the horizontalportions of the conformal silicon oxide layer, e. g. the portions beingarranged on the bottom of the upper portion of the deep trench. As aresult, the vertical portions of the silicon oxide layer remain on thesidewalls of the upper portion of the deep trench as a collar isolationin order to electrically isolate the further filling of the upperportion of the deep trench from the surrounding substrate of tehsemiconductor wafer. The bottom of the upper portion consisting of e. g.silicon oxide is opened to ensure the electrical accessibility of thepolysilicon in the lower portion of the trench. At a later phase of themanufacturing process of a DRAM device, an active area comprising anaccess transistor is formed within the substrate adjacent to the collarisolation.

[0003] The opening of the bottom surface of the trench must be performedwithout damaging the silicon nitride layer. For such removal of siliconoxide, a dry etch process using the etch gas C₄F₈ is already known. Theetching with C₄F₈ provides sufficient selectivity between silicon oxideand silicon nitride on the surface of the wafer and moreover provides agood etch stop performance on the bottom of the trench versus thepolysilicon filling material. A disadvantage of the etch gas C₄F₈,however, is that the very top section of the vertical part of the collaroxide is also etched to a larger extend due to the high silicon oxideetch rate of C₄F₈. This is particular true when used in capacitivelyworking plasma etch chambers, where a high sheath voltage causes a highion energy acceleration to the wafer surface which results in a highoxide etch rate. As a consequence said very top vertical section of thecollar oxide may be recessed to such an extend that the silicon oxid(PAD-oxide) hidden behind the collar oxide underneath the PAD-nitridesubsequent process steps. One of the subsequent process steps is anisotropic silicon wet etch which can undercut the PAD-silicon nitridelayer. The reliability of the process is less stable and the productionyield for DRAM devices is lower.

[0004] It is an object of the invention to provide a more stable andmore reliable process of forming an isolation layer on the sidewalls ofa trench, and it is a further object of the invention to provide a morestable and more reliable method of manufacturing a trench capacitorhaving such an isolation layer.

[0005] According to the invention, the object with respect to the methodof forming an isolation layer is achieved by a method of forming anisolation layer on the sidewalls of a trench comprising the steps of:providing a semiconductor wafer comprising a substrate having a firstisolation layer stack arranged on a main surface of the substrate andhaving a trench arranged in the substrate; depositing a second isolationlayer on the wafer; etching the wafer in a first step with a first etchgas composition comprising the gases CF₄ and SiF₄ and O₂; etching thewafer in a second etch step subsequent to said first etch step with asecond etch gas composition comprising the gas C₄F₈.

[0006] With respect to the method of manufacturing a trench capacitor,the object is achieved by a method of manufacturing a trench capacitorusing the aforementioned method, wherein the semiconductor wafer furthercomprises a deep trench having a lower portion with a dielectric layerarranged on its sidewalls and being filled with silicon and having anupper portion being arranged above the lower portion with said secondisolation layer being deposited on the sidewalls of said upper portionof said deep trench, and on the surface of said silicon arranged withinthe lower portion of said deep trench, and on the surface of said firstisolation layer stack.

[0007] The methods according to the invention benefit from a two-stepetch process for the removal of the horizontal portions of the secondisolation layer so that only the vertical portions remain, therebyforming a reliable collar oxide within the trench capacitor. The twosteps of the etch process have different properties that are adopted tothe progressing of the overall etch procedure. In this respect, thefirst etch step comprises a gas composition of CF₄, SiF₄ and O₂. Thisetch gas composition is known to etch silicon oxide, silicon nitride,and polysilicon at substantially the same rate, e.g. without substantialselectivity to each other. The etch rate of silicon oxide on the top ofthe wafer can be adjusted to be rather low. There is only little removalof silicon oxide on the top surface of the wafer so that it can beassured that there is always a sufficiently thick silicon oxide layer onthe silicon nitride layer that protects the silicon nitride. At thebottom of the trench, the etch rate of silicon oxide is ratherreasonable so that the silicon oxide is fully removed from theunderlying polysilicon filling material. As a result of the first etchstep using CF₄, SiF₄, and O₂, the silicon oxide on the bottom of thetrench is removed whereas a thin silicon oxide layer is still present onthe top main surface of the wafer protecting the silicon nitride.Moreover, the very top section of the vertical collar oxide is notdamaged. The different etch rates for silicon oxide on the bottom of thetrench and on the top surface are due to the fact that there is etchingand deposition of silicon oxide on the top surface and the trench bottomat the same time. At the trench bottom, the removal of silicon oxidedominates strongly over the deposition of silicon oxide, whereas at thetop surface the removal dominates only slightly over the depositionresulting in a higher overall oxide etch rate at the trench bottom thanat the top surface.

[0008] In the second etch step, the etch chemistry C₄F₈ which ispreferably diluted with CO or alternatively CO and O₂. This chemistry isknown for substantially high selectivity between silicon oxide andsilicon nitride so that the thin layer of silicon oxide that was left atthe end of the first etch step can be etched away in a rather uniformway without damaging the underlying silicon nitride layer. It is to benoted that the vertical portion of the silicon oxide layer at the verytop of the collar is recessed during the second etch step, due to theaggressiveness of the etch gas with respect to silicon oxide. The amountof recess, however, can be tolerated and is clearly within the thicknessof the silicon nitride layer and does definitely not reach below thesilicon nitride layer. The silicon substrate that is to be protected bythe collar oxide is, therefore, sufficiently covered at the very topportion of the trench where the silicon substrate contacts the siliconnitride layer so that there is no undercut by subsequent application ofwet etch chemicals.

[0009] As an overall consequence, the collar etch combines theadvantages of C₄F₈ and CF₄/SiF₄/O₂ etch properties for the etching ofthe collar oxide for the manufacturing of a trench capacitor. As aresult, a defined nitride surface is provided on the top of the waferhaving good uniformity of the nitride layer, the collar oxide is onlyrecessed little at the trench top and the collar oxide at the trenchbottom is opened perfectly.

[0010] The first etch step using CF₄/SiF₄/O₂ chemistry is finished whenthe silicon oxide is completely removed from the bottom of the trench.The second etch step using C₄F₈ chemistry is finished when the siliconoxide on top of the wafer, i. e. on top of the silicon nitride, iscompletely removed. The first etch step is run by time or endpoint whilethe second etch step is finished by endpoint. The second etch stepemploys a polymerizing chemistry. It is therefore advantageoustointroduce a subsequent sputter etch with O₂ to remove probable polymerresidues which is preferably followed by a wet etch clean.

[0011] As already stated, the isolation layer on the vertical sidewallsof the trench are particularly useful for a collar isolation oxide layerwhich isolates the upper part of a trench capacitor. The upper portionof the overall deep trench capacitor which is subject to theaforementioned etch processes serves to isolate the subsequentpolysilicon filling og the trench from the surrounding silicon substratewhere the active areas including access transistors are subsequentlyformed. The lower portion of the trench capacitor serves as the storagenode comprising the two electrodes of the capacitor.

[0012] The invention will now be described in detail with refernce tothe various figures within the drawings.

[0013]FIG. 1 shows a cross-section of a deep trench capacitor after thedeposition of a silicon oxide layer.

[0014]FIG. 2 shows a cross-section of the upper part of the deep trenchcapacitor after the first etch step using CF₄/SiF₄/O₂ and etchchemistry.

[0015]FIG. 3 shows the same cross-section at the end of the processafter the second etch step using C₄F₈ etch chemistry.

[0016]FIG. 4 shows a comparable cross-section after a conventional etchusing C₄F₈ etch chemistry only.

[0017] The cross-section depicted in FIG. 1 shows a semiconductor wafer10 having a silicon substrate 11. Within the substrate, a deep trench isformed having a lower portion 12 and an upper portion 13. The lowerportion 12 serves as the storage node of a capacitor arranged within thedeep trench. The storage node comprises a first capacitor electrode 15arranged within the substrate, a dielectric layer 14 covering thesidewalls of the lower portion 12 of the deep trench and a secondelectrode 16 arranged within the trench. The inner electrode 16 iscomprised of polysilicon. The polysilicon filling 16 as well as thedielectric layer 14 end within the lower portion 12 of the deep trench.The upper portion 13 of the deep trench is now subject to the subsequentprocess steps.

[0018] The semiconductor wafer has a PAD-silicon nitride layer 18 on itstop surface. The PAD nitride 18 remains during various process steps onthe layer and must, therefore, not be damaged by the etching steps. Aconformal oxide layer 17 is deposited on the wafer surface andconformally covers the top surface 172, the vertical sidewalls 174 ofthe upper portion 13 of the trench and the horizontal bottom 171 of thetrench forming a contact area to the polysilicon fill material of thelower portion 12 of the trench. The thickness of the deposited layer 17can be different on various areas of the wafer, e. g. the layer may beslightly thicker on the edge of the wafer compared to the center of thewafer. The goal is to remove all horizontal portions 172, 171 of thesilicon oxide so that only the vertical portions 174 remain within theupper portion 13 of the trench covering the vertical sidewalls of theportion 13 of the trench. The collar isolation 174 serves to isolate thesubsequently introduced polysilicon filling of the upper portion 13 ofthe trench from the surronding bulk silicon 11. Adjacent to the collaroxide, e. g. in the area 111 of the silicon substrate, a horizontal or avertical access transistor is to be formed. The deep trench capacitorand the access transistor together are considered a storage cell in adynamic random access memory (DRAM).

[0019] In a first etch step according to the invention, the result ofwhich is shown in FIG. 2, the horizontal surface 172 is partially etchedand th ehorizontal surface 171 of the silicon oxide layer 17 is fullyremoved, whereas the vertical portions 174 are still present. The firstetch step uses an etch gas composition with the chemicals CF₄, O₂, SiF₄(carbon tetra fluoride, oxygen, silicon tetra fluoride). The etching isperformed in a high-density plasma reactor. The etching opens the bottomof the trench and fully removes the previously present portion 171 ofthe silicon oxide layer and etches slightly into the polysilicon fillingof the lower portion of the trench leaving a bow-shaped surface. On thetop surface, the silicon oxide layer is only partially removed so thatthe underlying silicon nitride layer 18 is still completely covered bysilicon oxide 172. Since the etch rate of polysilicon is about threetimes higher than the etch rate of silicon oxide, the etch chemistryreadily attacks the polysilicon fill 16 within the trench and provides agood end point signal. In contrast, the etch process diminishes theoxide thickness on the top portion 172 on the wafer only slightly due toa combined etch/deposition reaction so that oveall a good opened collaris provided on the bottom of the trench. It is to be remarked that atthe very top section 173 of the collar oxide in the area where thecollar oxide contacts the nitride layer 18, the oxide layer is stillpresent. The removal of the silicon oxide portions 171, 172 may bevarying from the center to the edge of the wafer. In any case, there issufficient thickness of oxide 172 on top of the wafer so that thesilicon nitride layer 18 is not attacked during the first step.

[0020] After the situation shown in FIG. 2 has been reached by a fixedetch time or appropriate endpointing, the second etch step is startedusing different etch chemistries. The resulting structure is shown inFIG. 3. The etch gas composition during the second etch step uses C₄F₈,CO, and O₂ (cyclo butane octa fluoride, carbon monoxide, oxygen). Thisetch chemistry etches silicon oxide with reasonable selectivity tosilicon nitride. The thin silicon oxide layer 172 remaining at the endof the first etch step shown in FIG. 2 will now be fully removed fromthe silicon nitride layer 18. Due to the good selectivity betweensilicon oxide and silicon nitride almost no nitride is lost and the goodnitride uniformity achieved during the nitride deposition is retained.Due to the relatively high etch rate of silicon oxide, the top section173 of the vertical collar oxide is attacked at the same time. Theprocess time required for the second etch step, however, is establishedsuch that, although the top section 173 being recessed, the removal ofvertical collar oxide in the region 173 ends within the silicon nitridelayer 18 so that the PAD-oxide 19 underneath the PAD-nitride layer 18 iswell enough protected by a sufficiently thick vertical collar oxide sothat subsequent process steps, especially wet etch steps, do not attackthe silicon oxide 19 and under cut of the silicon nitride 18 is avoided.

[0021] As shown in FIG. 4, a prior art etch process which only uses C₄F₈ chemistry damages the vertical portion of the collar oxide on theuppermost section of the trench heavily so that the protection of thesilicon oxide 19 underneath the PAD-silicon nitride 18 in this area bythe collar oxide is not sufficient to avoid any further attack by asubsequent wet etch step. In the cross-section shown in FIG. 4, anundercut of silicon nitride would occur at location 191, which is theportion of the PAD-oxide 19 adjacent to the trench.

[0022] When compared to a conventional method shown in FIG. 4, thetwo-step etch process, the result of which is shown in FIG. 3, hassubstantially more collar oxide thickness left to protect the portion191 of the PAD-silicon oxide 19. Although the thickness of silicon oxideon the top surface is varying across the wafer after the first etch stepe. g. being thicker in the wafer center compared to the wafer etch, thehigh etch rate of the employed C₄F₈ chemistry for silicon oxide comparedto the low etch rate of silicon nitride enables to stop the second etchstep with substantially all silicon oxide being removed from the siliconnitride without reducing the thickness of the silicon nitride layer.

[0023] The surface of the silicon nitride layer 18 shown in FIG. 2 has agood uniformity in thickness. However, it may happen that polymerresidues are still present. In this case, the wafer surface on the topof the wafer, the trench sidewalls and especially the trench bottom mustbe cleaned with an additional O₂-sputter etch which is preferablyfollowed by wet clean. In particular, the surface 161 of the innerelectrode 16 and the top surface of the PAD-nitride 18 are cleaned fromthe polymer residues from the second etch step.

[0024] Finally, all horizontal layer portions of the previouslydeposited silicon oxide layer 17 are removed and only the verticalportions 174 of the silicon oxide layer remain after the above describedtwo-step etch process forming a collar isolation that isolates thesubsequently to be formed inner filling of the upper portion 13 of thetrench from the surrounding silicon substrate 11 that will furthercontain active areas with access transistors. The inner portion of thetrench will be further filled with doped polysilicon in order to providea conducting inner electrode of the trench capacitor. The subsequentpolysilicon fill (not shown in the figure) will then be contacted to theactive area in the semiconductor substrate, e. g. by a buried strap.

[0025] The invention is referably applicable to smaller devicestructures, e. g. down to and less than 110 nm (nanometers). The processperformance and the reliability of the manufactured products isincreased. The process can be implemented on various plasma etchingtools, e. g. RIE- or high-density plasma etchers.

[0026] Attached are various examples for process parameters for etching300 mm-wafers in a process according to the invention.

[0027] Example for the first etch step: Total gas flow: 150-400 sccmGases: C₄F₈, Ar (optional CO and/or O₂) Molar fraction C₄F₈: 0.01-0.10

[0028] 3. Example: Tool: 300 mm dual frequency plasma etcher Power top:500-1500 W Power bottom: 0-500 W Pressure: 100-400 mTorr Total gas flow:500-1000 sccm Gases: C₄F₈, Ar (optional CO and/or O₂) Molar fractionC₄F₈: 0.01-0.10

[0029] 4. Example: Tool: 300 mm magnetically enhanced reacitve ionplasma etcher Power: 1000-2500 W Magnetic field: 0-20 G Pressure: 50-150m Torr Total gas flow: 200-500 sccm Gases: C₄F₈, Ar (optional CO and/orO₂) Molar fraction C₄F₈: 0.01-0.10

[0030] List of reference numerals 10 semiconductor wafer 11 substrate111 active area 112, 113 portions of substrate 12 lower portion oftrench 13 upper portion of trench 14 dielectric 15, 16 capacitorelectrodes 17 silicon oxide layer 171 silicon oxide layer at trenchbottom 172 silicon oxide layer at wafer surface 173 silicon oxide layerat upper edge 174 silicon oxide layer at collar 18 silicon nitridelayer, PAD-nitride 19 silicon oxide layer, PAD-oxide 161 surface ofcapacitor electrode 191 silicon oxide layer adjacent to trench

I/We claim
 1. A method of forming an isolation layer on the sidewalls of a trench, comprising: a semiconductor wafer comprising a substrate having a first isolation layer stack arranged on a main surface of the substrate and having a trench arranged in the substrate; depositing a second isolation layer on the wafer etching the wafer with a first etch gas composition comprising the gases CF₄ and SiF₄ and 0 ₂; and etching the wafer in a second etch step subsequent to the first etch step with a second etch gas composition comprising the gas C₄F₈.
 2. The method according to claim 1, wherein the second etch gas compositions further comprises at least one of the gases CO and 0 ₂.
 3. The method according to claim 1, wherein the first etch step is stopped when a portion of the second isolation layer, which is arranged on the bottom of the trench, is removed.
 4. The method according to claim 3, wherein the first etch step is stopped when a portion of the second isolation layer, which is arranged on the first isolation layer stack completely covers the first isolation layer stack.
 5. The method according to claim 1, the first isolation layer stack comprises silicon nitride and the second isolation layer comprises silicon oxide.
 6. The method according to claim 1, further comprising sputter etching using 0 ₂ to clean the surface of a capacitor electrode arranged within the trench and the surface of the first isolation layer stack from residues of the second etch step.
 7. A method of manufacturing a trench capacitor, comprising: a method of forming an isolation layer on the sidewalls of a trench, providing a semiconductor wafer comprising a substrate having a first isolation layer stack arranged on a main surface of the substrate and having a trench arranged in the substrate; depositing a second isolation layer on the wafer etching the wafer with a first etch gas composition comprising the gases CF₄ and SiF₄ and 0 ₂; and etching the wafer in a second etch step subsequent to the first etch step with a second etch gas composition comprising the gas C₄F₈; wherein the semiconductor wafer further comprises a deep trench having a lower portion with a dielectric layer arranged on its sidewalls, the deep trench being filled with silicon, the deep trench having an upper protion being arranged above the lower portion, the second isolation layer being deposited onthe sidewalls of the upper portion of th edeep trench, on the surface of the silicon arranged within the lower portion of the deep trench, and on the surface of the first isolation layer stack.
 8. The method according to claim 7, wherein the second isolation layer is a collar isolation and the upper portion of the deep trench is further filled with doped silicon.
 9. The method according to claim 6, wherein the sputter etching is subsequent to the second etch step.
 10. The method according to claim 7, wherein the second etch gas compositions further comprises at least one of the gases CO and O₂.
 11. The method according to claim 7, wherein the first etch step is stopped when a portion of the second isolation layer, which is arranged on the bottom of the trench, is removed.
 12. The method according to claim 11, wherein the first step is stopped when a portion of the second isolation layer, which is arranged on the first isolation layer stack completely covers the first isolation layer stack.
 13. The method according to claim 7, the first isolation layer stack comprises silicon nitride and the second isolation layer comprises silicon oxide.
 14. The method according to claim 7, further comprising a sputter etching using 0 ₂ to clean the surface of a capacitor electrode arranged within the trench and the surface of the first isolation layer stack from residues of the second etch step.
 15. The method according to claim 14, wherein the sputter etching is subsequent to the second etch step. 